Viraj is an MTech student at IIT Kharagpur, passionate about applying AI in modern chip design and verification. As an RTL verification intern, he utilized SystemVerilog to enhance code efficiency by 30%. His skills include C++, SystemVerilog, and Fortran, complemented by several certifications in microelectronics and semiconductor devices.
Outside of his technical pursuits, Viraj is a cyclist, a hobby he has maintained since childhood. He shows appreciation for community initiatives, publicly supporting events like a university blood donation drive. He also follows the latest scientific research, attending webinars on topics like quantum engineering and environmental sustainability.
Unique fact: Viraj is a two-time qualifier for the Graduate Aptitude Test in Engineering (GATE), a highly competitive national-level examination in India.
Read the full overview →Behavioral traits and communication patterns that shape how this person evaluates opportunities, builds trust, and makes decisions in professional settings.
Dominance, influence, steadiness, and calculativeness scores with guidance on how this person prefers to communicate and decide.
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