MADDALI YASWANTH
Login to view DISC.Maddali Yaswanth is a Senior ASIC Digital Verification Engineer at Synopsys, specializing in UVM-based verification for complex PCIe and multi-protocol subsystems. He holds a Master of Technology from the National Institute of Technology Puducherry and has co-authored a published research paper on neural networks.
Outside of his engineering work, he is a passionate and accomplished cricket player. He has been recognized with multiple awards in corporate and city leagues, including "Best bowler of the series" and several "Man of the Match" honors, highlighting his competitive spirit and athletic talent.
He co-authored an IEEE conference paper on using Hopfield Neural Networks for digit classification.
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