Shridhar P Bhat in

Shridhar P Bhat

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Layout/Library Design Engineer at Intel Corporation
📍 Greater Bengaluru Area, India

Shridhar P Bhat is an experienced Layout and Library Design Engineer at Intel, specializing in standard cell and memory layout architecture. Certified with an Advanced Diploma in Full-Custom ASIC design, his work spans advanced nodes like Intel 18A and 14A, leveraging industry-standard EDA tools.

He has extensive hands-on experience solving DRC and LVS issues across a wide range of semiconductor process nodes, from 180nm down to 16nm.

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Experience
6 Years
Current Role
Layout/Library Design Engineer
Job Level
Middle
Location
Greater Bengaluru Area, India
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Priorities

Topics Shridhar cares about

Custom Layout Design
His career focuses on Standard Cell and Memory Layout Design at Intel, demonstrating deep expertise in full-custom layout techniques and architecture.
Process Node Technology
He possesses hands-on experience with a wide spectrum of nodes, from legacy 180nm to advanced Intel 18A and 14A, indicating a focus on semiconductor evolution.
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Career

Work history

9-2022
Layout/Library Design Engineer
Intel Corporation
2-2021 - 8-2022
Platform/System Validation Engineer
Intel Corporation
7-2019 - 2-2021
Memory layout Engineer
leadIC Design Pvt Ltd
10-2017 - 4-2018
Trainee
RV-VLSI VLSI and Embedded Systems Design Center
In the press

Media appearances

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Education
2017 - 2018
Advanced Diploma in Full-Custom layout design
RV-VLSI Design Center
2013 - 2017
BE - Bachelor of Engineering
APS college of Engineering Bangalore
Social presence
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Behavioral profile

DISC profile (public)

DISC behavioral profile

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