Sheetal Rana
Login to view DISC.Sheetal Rana is a Digital Design Engineer at NXP Semiconductors with expertise in the VLSI industry, particularly in Design for Test (DFT) and RTL Design. A graduate of Indira Gandhi Delhi Technical University for Women, she has hands-on experience in ATPG simulations, scan insertion, and synthesis.
Beyond her core engineering role, Sheetal is passionate about fostering talent. She has experience leading a delivery team focused on talent acquisition and has dedicated time to helping new graduates and women restart their careers in the tech industry. She is also committed to continuous learning.
She recently represented NXP India at the Global Investors Meet to foster collaborations and investments.
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